This invention relates to an improved semiconductor device and method for fabricating that device, and more particularly to an insulated gate field effect transistor having a metal silicide gate electrode and self-aligned metal silicide contacts to the source and drain regions.
A widely used insulated gate field effect transistor (IGFET) utilizes a doped polycrystalline silicon region as a gate electrode. In many applications such a silicon gate IGFET is totally adequate but in certain applications, particularly high performance circuits and those circuits using a large array of such transistors, the resistance along the doped polycrystalline silicon can be a factor limiting the performance of the circuit. In a particular configuration, for example, a number of such polycrystalline silicon gates may be tied together by a polycrystalline silicon interconnection to form a word line. The speed with which that word line can be charged and discharged can be limited by the RC time constant associated with that line. The time constant, in turn, is directly proportional to the resistance of the polycrystalline silicon line. High resistance polycrystalline silicon thus leads to a large time constant and limits circuit performance. A further limitation of the performance of prior art IGFET circuits is the area occupied by each individual transistor. Large area devices lead to circuits having a large total area which are difficult to fabricate with an acceptable yield. Large devices also imply large junction area and the large junction area results in a large junction capacitance which must be charged and discharged as the circuit functions. The large junction capacitance in turn leads, again, to degraded circuit performance.
The conventional silicon gate IGFET process results in large devices for reasons which are at least indirectly related to the lack of a totally self-aligned process. In the standard process, lateral misalignment of the gate electrode with respect to the diffused source and drain regions can result in one of the regions being narrower than the design width. The resistance along this narrower than designed region can be intolerably high and can lead, because of distributed resistance effects, to the inoperation of the extremities of the device. To overcome this effect the diffused regions must be designed overly large so that even in the event of a misalignment the resistance will not be too high to limit operation of the device. This results in overly large devices. A further solution for overcoming this problem is to very heavily dope the diffused source and drain regions to increase their conductivity. But there are two potential problems with this solution. First, the heavily doped region may have undesirable breakdown characteristics or undesirable minority carrier lifetime characteristics associated therewith because of the degeneracy required of the region. Secondly, if the regions are doped by ion implantation, the heavy doping may require too long an implant time since implant dose is directly proportional to time. A still further solution involves metallizing the source and drain regions. This solution too, however, is unworkable since it requires contact openings to the source and drain regions, and thus requires the alignment of these contact openings and the metal itself with respect to the gate electrode. Tolerances associated with these two alignment steps require the useage of too much surface area on the integrated circuit chip.
Accordingly, it is apparent that a need existed in the semiconductor industry for an improved device and method of fabrication, especially in the high performance or high density applications of semiconductor devices. This need cannot be met by any of the processes or designs heretofore existing.
Therefore, it is an object of this invention to provide a device and a method of fabricating that device which is capable of increased performance and increased packing density.
It is a further object of this invention to provide an improved device and self-aligned method for fabricating that device.
It is a still further object of this invention to provide a self-aligned process for fabricating a device having a high conductivity gate electrode and high conductivity source and drain electrodes.
It is another object of this invention to provide a high yielding device fabrication process that uses reduced levels of ion implantation.
It is still another object of this invention to provide a high density process for fabricating smaller, more compact devices.